In the fabrication of semiconductor chips, bonding pads are commonly used to facilitate the wire bonding process which provides electric connections to electrical terminals on the associated devices. The conventional bonding pad design to deposit a square metal pad, about 100 .mu.m by 100 .mu.m, on the semiconductor surface. During the wire bonding process to attach the solder bumps, however, the bonding pad can often be lifted off due to the high pulling force or inadequate adhesion between the metal bonding pad and the semiconductor surface. As the density of semiconductor devices becomes increasingly higher resulting in increased stress per unit area, the bonding pad peeling off problems become more profound. This is further complicated by the fact that, in order to save fabrication cost and remain competitive, inexpensive metals such as aluminum have been prevalently used as the metal bonding pad and wiring material, replacing the much more expensive gold. Due to its higher thermal expansion coefficient, the use of aluminum wire and bonding pad causes substantially greater stress to be imposed, thus exacerbates the problem.
One commonly utilized approach to ameliorate the bonding pad peel-off problem is to form a passivation layer around the periphery of the bonding pad. The passivation layer causes the metal bonding pad to be partially encapsulated, at least at the periphery thereof. The encroachment area formed by the passivation layer helps the metal bonding pad to stay in place during the wire bonding process. However, due to the significant difference between the thermal expansion coefficients of the metal bonding pad and the passivation layer, which is typically a non-metal dielectric material such as silicon nitride or silicon oxide, the metal bonding pad can often crack during the deposition of the dielectric passivation layer or during the post passivation annealing process. Typically, the passivation layer is formed by PECVD (plasma enhanced chemical vapor deposition) process at a temperature of about 400.degree. C. The metal bonding pad will be subject to a significant temperature raise both during and after the passivation layer deposition. The large difference in the thermal expansion coefficients between the passivation layer and the metal bonding pad will exert a high mechanical stress on the metal bonding pad. If the stress is high enough and if the thickness of the bonding pad is not thick enough, cracks will develop, resulting in substantially reduced adhesion between metal bonding pad and the semiconductor chip.
Several prior art references have taught various ways to solve the bonding pad peel-off problem. For example, U.S. Pat. No. 5,734,200, the content thereof is incorporated by reference, discloses a polycide bonding pad structure for use with an aluminum wire that resists stresses that would otherwise peel the pad from the substrate. The bonding pad structure contains a polysilicon layer adhered to an insulating layer, typically a field oxide layer formed of thermal silicon oxide, on a semiconductor substrate, an overlying refractory metal polycide layer, such as tungsten, titanium, platinum or palladium, a second polysilicon layer, a refractory metal layer, and a thick aluminum alloy bonding pad. The purpose of this relatively complex bonding pad structure is to ameliorate the use of Al wires (in place of the much more expensive gold wires), which impose greatly increased stress due to its greater coefficient of thermal expansion on the thermal bonding pads resulting in drastically reduced yield.
U.S. Pat. No. 5,736,791, the content thereof is incorporated by reference, discloses a semiconductor and an associated bonding pad structure of a multilayered wiring structure. The bonding pad structure comprises a first wiring layer and a second wiring layer which is located over the first wiring layer and an interlayer insulation layer between the wiring layers which has an electrically conductive component so as to electrically connect the wiring layers through a plurality of via holes. The first wiring layer has a wiring pattern including a plurality of spaced apart portions, each of which is connected to the second wiring layer through an appropriate via hole. The bond pad structure is such that no crack is formed in the interlayer insulation layer during wiring bonding.
U.S. Pat. No. 5,773,899, the content thereof is also incorporated by reference, discloses a bonding pad for a semiconductor structure which prevents damage during a bonding process. The semiconductor chip has conductive regions interconnected by a metal pattern, and a metal region is disposed over the metal pattern. The metal region forms the bonding pad over the conductive regions. Furthermore, the metal region is in direct contact with the metal pattern for substantially the whole bonding pad area. With the arrangement disclosed in the '899 patent, the metal region absorbs mechanical stress induced when a bonding wire is bonded to the metal region during the bonding process. The metal region should be sufficient thick so as not to be perforated during the bonding process and that the metal pattern is not damaged.
The above-mentioned prior art patents have their respective advantages and disadvantages. However, due to the immense pressure faced by semiconductor manufacturers to constantly cut the production cost, it is highly desirable to explore other methods and bonding pad designs that may provide a more cost-effective way to solve the bonding pad peeling off problems and improve the production yield. Most preferably, the improved bonding pad design should be able to be implemented easily and without incurring large additional costs.